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: Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction.
VTS
2001
: On minimizing the number of test points needed to achieve complete robust path delay fault testability.
VTS
1996
: Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems
(TCAD)
28(3):426-432 (2009)
: Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions.
IEEE Trans. on CAD of Integrated Circuits and Systems
(TCAD)
28(1):121-129 (2009)
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circuits combinational compaction coverage delay design fault generation method multiple path procedure scan sequences sequential sets synchronous test testing transition