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Irith Pomeranz, Sudhakar M. Reddy: On Static Compaction of Test Sequences for Synchronous Sequential Circuits. DAC 1996

Janak H. Patel, Steven S. Lumetta, Sudhakar M. Reddy: Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns. VTS 2003

Huaxing Tang, Sudhakar M. Reddy, Irith Pomeranz: On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. ITC 2003

Yuan Cai, Marcus T. Schmitz, Alireza Ejlali, Bashir M. Al-Hashimi, Sudhakar M. Reddy: Cache size selection for performance, energy and reliability of time-constrained systems. ASP-DAC (ASPDAC) 2006

Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni: Vertex Splitting in Dags and Applications to Partial Scan Designs and Lossy Circuits. Int. J. Found. Comput. Sci. (IJFCS) 9(4):377-398 (1998)

Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara: Compact test generation for bridging faults under I/sub DDQ/ testing. VTS 1995

Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy: COMPACTEST: a method to generate compact test sets for combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD) 12(7):1040-1049 (1993)

Lakshmi N. Reddy, Irith Pomeranz, Sudhakar M. Reddy: COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits. ICCAD 1992

Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy: COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits. ITC 1991

Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy: Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy. ICCAD 1991

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